10.
-
module kod (clk, reset_n, x, z);
input x, clk, reset_n;
output reg z;
reg [2:0] state;
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) state <= S3; else state <= fsm_next_state(state, x);
...
...
bla bla bla
diye devam eder.
...
...
...
endmodule
